Pattern Based Cache Coherency Architecture for Embedded Manycores
نویسندگان
چکیده
منابع مشابه
Ip - Esc ’ 11 Co - Designed Cache Coherency Architecture for Embedded Multicore Systems
One of the key challenges in chip multi-processing is to provide a programming model that manages cache coherency in a transparent and efficient way. A large number of applications designed for embedded systems are known to read and write data following memory access patterns. Memory access patterns can be used to optimize cache consistency by prefetching data and reducing the number of memory ...
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ژورنال
عنوان ژورنال: Procedia Computer Science
سال: 2016
ISSN: 1877-0509
DOI: 10.1016/j.procs.2016.05.481